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flash-erasable reprogrammable cmos pal ? device palce16v8 cypress semiconductor corporation ? 3901 north first street ? san jose , ca 95134 ? 408-943-2600 document #: 38-03025 rev. *a revised april 22, 2004 features ? active pull-up on data input pins ? low power version (16v8l) ? 55 ma max. commercial (10, 15, 25 ns) ? 65 ma max. industrial (10, 15, 25 ns) ? 65 ma military (15 and 25 ns) ? standard version has low power ? 90 ma max. commercial (10, 15, 25 ns) ? 115 ma max. commercial (7 ns) ? 130 ma max. military/industrial (10, 15, 25 ns) ? cmos flash technology for electrical erasability and reprogrammability ? pci-compliant ? user-programmable macrocell ? output polarity control ? individually selectable for registered or combina- torial operation ? up to 16 input terms and eight outputs ? 7.5 ns com?l version 5 ns t co 5 ns t s 7.5 ns t pd 125-mhz state machine ? 10 ns military/industrial versions 7 ns t co 10 ns t s 10 ns t pd 62-mhz state machine ? high reliability ? proven flash technology ? 100% programming and functional testing functional description the cypress palce16v8 is a cmos flash electrical erasable second-generation programmable array logic device. it is implemented with the familiar sum-of-product (and-or) logic structure and the programmable macrocell. 88 888 88 8 10 987 65 4321 11 12 13 14 15 16 17 18 19 20 programmable and array (64 x 32) macrocell macrocell macrocell macrocell macrocell macrocell macrocell macrocell gnd i 8 i 7 i 6 i 5 i 4 i 3 i 2 i 1 clk/i 0 oe/i 9 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 v cc logic block diagram ( pdip /c dip ) pin configurations plcc/lcc top view 18 17 16 15 14 4 5 6 7 8 9 10111213 321 19 i i clk/i i/o 20 v cc oe/i i/o i/o clk/i 0 i 1 i 2 i 3 i 4 i 8 gnd oe/i 9 v cc i/o 7 i/o 6 i/o 4 i/o 3 i/o 2 i/o 0 i/o 5 i 5 i 6 i 7 i/o 1 1 2 3 4 5 6 7 8 9 10 11 12 16 15 14 13 17 20 19 18 dip i 3 i 4 i 5 i 6 i 7 2 1 0 7 i/o 6 i/o 4 i/o 3 i/o 2 i/o 5 8 i gnd 9 0 1 top view
palce16v8 document #: 38-03025 rev. *a page 2 of 13 functional description the palce16v8 is executed in a 20-pin 300-mil molded dip, a 300-mil cerdip, a 20-lead square ceramic leadless chip carrier, and a 20-lead square plastic leaded chip carrier. the device provides up to 16 inputs and 8 outputs. the palce16v8 can be electrically erased and reprogrammed. the programmable macrocell enables the device to function as a superset to the familiar 20-pin plds such as 16l8, 16r8, 16r6, and 16r4. the palce16v8 features 8 pr oduct terms per output and 32 input terms into the and array. the first product term in a macrocell can be used either as an internal output enable control or as a data product term. there are a total of 18 architecture bits in the palce16v8 macrocell; two are global bits that apply to all macrocells and 16 that apply locally, two bits per macrocell. the architecture bits determine whether the macrocell functions as a register or combinatorial with inverting or noninverting output. the output enable control can come from an external pin or internally from a product term. the output can also be permanently enabled, functioning as a dedicated out put or permanently disabled, functioning as a dedicated input. feedback paths are selectable from either the in put/output pin associated with the macrocell, the input /output pin associated with an adjacent pin, or from the macrocell register itself. power-up reset all registers in the palce16v8 power-up to a logic low for predictable system initializatio n. for each register, the associated output pin will be high due to active-low outputs. electronic signature an electronic signature word is provided in the palce16v8 that consists of 64 bits of programmable memory that can contain user-defined data. security bit a security bit is provided that defeats the readback of the internal programmed pattern wh en the bit is programmed. low power the cypress palce16v8 provides low-power operation through the use of cmos technology, and increased testability with flash reprogrammability. product term disable product term disable (ptd) fuses are included for each product term. the ptd fuses allow each product term to be individually disabled. selection guide generic part number t pd ns t s ns t co ns i cc ma com?l/ind mil com?l/ind mil com?l/ind mil com?l mil/ind palce16v8-5 5 3 4 115 palce16v8-7 7.5 7 5 115 palce16v8-10 10 10 10 10 7 10 90 130 palce16v8-15 15 15 12 12 10 10 90 130 palce16v8-25 25 25 15 20 12 12 90 130 palce16v8l-15 15 15 12 12 10 12 55 65 palce16v8l-25 25 25 15 20 12 20 55 65 shaded areas contain preliminary information. configuration table cg 0 cg 1 cl0 x cell configuration devices emulated 0 1 0 registered output registered med pals 0 1 1 combinatorial i/o registered med pals 1 0 0 combinatorial output small pals 1 0 1 input small pals 1 1 1 combinatorial i/o 16l8 only
palce16v8 document #: 38-03025 rev. *a page 3 of 13 macrocell q q d clk 1 1 0 0 1 x cl1 x 0 1 x 0 1 1 i/o x from adjacent pin cl0 x cg 1 for pin 13 to 18 cg 0 for pin 12 and 19 1 0 0 1 1 1 0 0 0 1 x 0 1 1 oe v cc to adjacent macrocell cl0 x cg 1 v cc
palce16v8 document #: 38-03025 rev. *a page 4 of 13 maximum ratings (above which the useful life may be impaired. for user guide- lines, not tested.) storage temperature ................................. ?65 c to +150 c ambient temperature with power applied............................................. ?55 c to +125 c supply voltage to ground potential (pin 24 to pin 12) ........................................... ?0.5v to +7.0v dc voltage applied to outputs in high-z state ............................................... ?0.5v to +7.0v dc input voltage ............................................?0.5v to +7.0v output current into outputs (low)............................. 24 ma dc programming voltage............................................. 12.5v latch-up current .................................................... > 200 ma operating range range ambient temperature v cc commercial 0 c to +75 c 5v 5% military [1] ?55 c to +125 c 5v 10% industrial ?40 c to +85 c5v 10% electrical characteristics over the operating range [2] parameter description test conditions min. max. unit v oh output high voltage v cc = min., v in = v ih or v il i oh = ?3.2 ma com?l 2.4 v i oh = ?2 ma mil/ind v ol output low voltage v cc = min., v in = v ih or v il i ol = 24 ma com?l 0.5 v i ol = 12 ma mil/ind v ih input high level guaranteed input logical high voltage for all inputs [3] 2.0 v v il [4] input low level guaranteed input logical low voltage for all inputs [3] ?0.5 0.8 v i ih input or i/o high leakage current 3.5v < v in < v cc 10 a i il [5] input or i/o low leakage current 0v < v in < v in (max.) ?100 a i sc output short circuit current v cc = max., v out = 0.5v [6, 7] ?30 ?150 ma i cc operating power supply current v cc = max., v il = 0v, v ih = 3v, output open, f = 15 mhz (counter) 5, 7 ns com?l 115 ma 10, 15, 25 ns 90 ma 15l, 25l ns 55 ma 10, 15, 25 ns mil/ind 130 ma 15l, 25l ns mil. 65 ma 15l, 25l ns ind. 65 ma capacitance [7] parameter description test conditions typ. unit c in input capacitance v in = 2.0v @ f = 1 mhz 5 pf c out output capacitance v out = 2.0v @ f = 1 mhz 5 pf endurance characteristics [7] parameter description test conditions min. max. unit n minimum reprogramming cycles normal programming conditions 100 cycles notes: 1. t a is the ?instant on? case temperature. 2. see the last page of this specification for group a subgroup testing information. 3. these are absolute values with respect to device ground. a ll overshoots due to system or tester noise are included. 4. v il (min.) is equal to ?3.0v for pulse durations less than 20 ns. 5. the leakage current is due to the internal pull-up resistor on all pins. 6. not more than one output should be tested at a time. duration of the short circuit should not be more than one second. v out = 0.5v has been chosen to avoid test problems caused by tester ground degradation. 7. tested initially and after any design or process changes that may affect these parameters.
palce16v8 document #: 38-03025 rev. *a page 5 of 13 ac test loads and waveforms specification s 1 c l commercial military measured output value r 1 r 2 r 1 r 2 t pd , t co closed 50 pf 200 ? 390 ? 390 ? 750 ? 1.5v t pzx , t ea z h: open z l: closed 1.5v t pxz , t er h z: open l z: closed 5 pf h z: v oh ? 0.5v l z: v ol + 0.5v commercial and industrial switching characteristics [2] parameter description 16v8-5 16v8-7 16v8-10 16v8-15 16v8-25 unit min. max. min. max. min. max. min. max. min. max. t pd input to output propagation delay [8, 9] 1 5 3 7.5 3 10 3 15 3 25 ns t pzx oe to output enable 1 6 6 10 15 20 ns t pxz oe to output disable 1 5 6 10 15 20 ns t ea input to output enable delay [7] 1 6 9 10 15 25 ns t er input to output disable delay [7, 10] 1 5 9 10 15 25 ns t co clock to output delay [8, 9] 1 42527210212ns t s input or feedback set-up time 3 5 7.5 12 15 ns t h input hold time 0 00 0 0 ns t p external clock period (t co + t s ) 7 10 14.5 22 27 ns shaded areas contain preliminary information. notes: 8. min. times are tested initially and after any design or process changes that may affect these parameters. 9. this specification is guaranteed for all devi ce outputs changing state in a given access cycle. 10. this parameter is measured as the time after oe pin or internal disable input disables or enables the output pin. this delay is measured to the point at which a previous high level has fallen to 0.5 volts below v oh min. or a previous low level has risen to 0.5 volts above v ol max. 11. this specification indicates the guaran teed maximum frequency at which a state machine configuration with external feedback can operate. 12. this specification indicates the guaranteed maximum fre quency at which the device can operate in data path mode. 13. this specification indicates the guarante ed maximum frequency at which a state machine configuration with internal only feed back can operate. 14. this parameter is calculated from the clock period at f max internal (1/f max3 ) as measured (see note 7 above) minus t s . 90% 10% 3.0v gnd 90% 10% all input pulses <2ns <2ns output r2 r1 c l s1 5v test point
palce16v8 document #: 38-03025 rev. *a page 6 of 13 t wh clock width high [7] 3 46 8 12ns t wl clock width low [7] 3 46 8 12ns f max1 external maximum frequency (1/(t co + t s )) [7, 11] 143 100 69 45.5 37 mhz f max2 data path maximum frequency (1/(t wh + t wl )) [7, 12] 166 125 83 62.5 41.6 mhz f max3 internal feedback maximum frequency (1/(t cf + t s )) [7, 13] 166 125 74 50 40 mhz t cf register clock to feedback input [7, 14] 3 3 6 8 10 ns t pr power-up reset time [7] 1 11 1 1 s commercial and industrial switching characteristics (continued) [2] parameter description 16v8-5 16v8-7 16v8-10 16v8-15 16v8-25 unit min. max. min. max. min. max. min. max. min. max. military switching characteristics [7] 16v8-10 16v8-15 16v8-25 parameter description min. max. min. max. min. max. unit t pd input to output propagation delay [8, 9] 310315325ns t pzx oe to output enable 10 15 20 ns t pxz oe to output disable 10 15 20 ns t ea input to output enable delay [7] 10 15 25 ns t er input to output disable delay [7, 10] 10 15 25 ns t co clock to output delay [8, 9] 27210212ns t s input or feedback set-up time 10 12 15 ns t h input hold time .5 .5 .5 ns t p external clock period (t co + t s )17 22 27 ns t wh clock width high [7] 6812ns t wl clock width low [7] 6812ns f max1 external maximum frequency (1/(t co + t s ) [7, 11] 58 45.5 37 mhz f max2 data path maximum frequency (1/(t wh + t wl )) [7, 12] 83 62.5 41.6 mhz f max3 internal feedback maximum frequency (1/(t cf + t s )) [7, 13] 62.5 50 40 mhz t cf register clock to feedback input [7, 14] 6810ns t pr power-up reset time [7] 111 s
palce16v8 document #: 38-03025 rev. *a page 7 of 13 switching waveform power-up reset waveform t s t h t wl t wh t p t co t pd t pxz ,t er inputs, i/o, registered feedback cp registered outputs combinatorial outputs t pxz ,t er t ea ,t pzx t ea ,t pzx [10 ] [10] [10] [10] t pr power clock t s t wl 10% registered active low outputs supply voltage t pr max = 1 s 90% v cc
palce16v8 document #: 38-03025 rev. *a page 8 of 13 functional logic diagram for palce16v8 0 1 16 20 24 28 00 12 8 431 19 23 27 15 11 7 3 2 19 0 16 202428 12 8 431 19 23 27 15 11 7 3 11 mc7 cl1=2048 cl0=2120 ptd=2128 -2135 3 18 mc6 cl1=2049 cl0=2121 ptd=2136 -2143 4 17 mc5 cl1=2050 cl0=2122 ptd=2144 -2151 5 16 mc4 cl1=2051 cl0=2123 ptd=2152 -2159 6 15 mc3 cl1=2052 cl0=2124 ptd=2160 -2167 7 14 mc2 cl1=2053 cl0=2125 ptd=2168 -2175 8 13 mc1 cl1=2054 cl0=2126 ptd=2176 -2183 9 12 mc0 cl1=2055 cl0=2127 ptd=2184 -2191 10 user electronic signature row byte 0 byte 1byte 2byte 3byte 4 byte 5 byte 6 byte 7 2056 2064 2072 2080 2088 2096 2104 2112 2119 msb msb lsb lsb cg 0 =2192 cg 1 =2193 20 v cc product line first cell numbers pin numbers input line numbers pin numbers 32 96 160 224 64 128 192 256 288 352 416 480 320 384 448 512 544 608 672 736 576 640 704 768 800 864 928 992 832 896 960 1024 1056 1120 1184 1248 1088 1152 1216 1280 1312 1376 1440 1504 1344 1408 1472 1536 1568 1632 1696 1760 1600 1664 1728 1792 1824 1888 1952 2016 1856 1920 1984 global arch bits
palce16v8 document #: 38-03025 rev. *a page 9 of 13 ordering information i cc (ma) t pd (ns) t s (ns) t co (ns) ordering code package name package type operating range 115 5 3 4 palce16v8-5jc j61 20-lead plastic leaded chip carrier commercial 115 7.5 5 5 palce16v8-7jc j61 20-lead plastic leaded chip carrier commercial palce16v8-7pc p5 20-lead (300-mil) molded dip 90 10 7.5 7 palce16v8-10jc j61 20-lead plastic leaded chip carrier palce16v8-10pc p5 20-lead (300-mil) molded dip 130 10 7.5 7 palce16v8-10ji j61 20-lead plastic leaded chip carrier industrial palce16v8-10pi p5 20-lead (300-mil) molded dip 130 10 10 7 palce16v8-10dmb d6 20-lead (300-mil) cerdip military palce16v8-10lmb l61 20-pin square leadless chip carrier 90 15 12 10 palce16v8-15jc j61 20-lead plastic leaded chip carrier commercial palce16v8-15pc p5 20-lead (300-mil) molded dip 130 15 12 10 palce16v8-15pi p5 20-lead(300mil) molded dip industrial palce16v8-15dmb d6 20-lead (300-mil) cerdip military palce16v8-15lmb l61 20-pin square leadless chip carrier 90 25 15 12 palce16v8-25jc j61 20-lead plastic leaded chip carrier commercial palce16v8-25pc p5 20-lead (300-mil) molded dip 130 25 15 12 palce16v8-25ji j61 20-lead plastic leaded chip carrier industrial palce16v8-25dmb d6 20-lead (300-mil) cerdip military palce16v8-25lmb l61 20-pin square leadless chip carrier 55 10 7.5 7 palce16v8l-10jc j61 20-lead plastic leaded chip carrier commercial palce16v8l-10pc p5 20-lead (300-mil) molded dip 65 10 10 7 palce16v8l-10ji j61 20-lead plastic leaded chip carrier industrial palce16v8l-10pi p5 20-lead (300-mil) molded dip 55 15 12 10 palce16v8l-15jc j61 20-lead plastic leaded chip carrier commercial palce16v8l-15pc p5 20-lead (300-mil) molded dip 65 15 12 10 palce16v8l-15dmb d6 20-lead (300-mil) cerdip military palce16v8l-15lmb l61 20-pin square leadless chip carrier 55 25 15 12 palce16v8l-25jc j61 20-lead plastic leaded chip carrier commercial palce16v8l-25pc p5 20-lead (300-mil) molded dip military 65 25 15 12 palce16v8l-25dmb d6 20-lead (300-mil) cerdip palce16v8l-25lmb l61 20-pin square leadless chip carrier shaded areas contain preliminary information.
palce16v8 document #: 38-03025 rev. *a page 10 of 13 military specifications group a subgroup testing dc characteristics parameter subgroups v oh 1, 2, 3 v ol 1, 2, 3 v ih 1, 2, 3 v il 1, 2, 3 i ix 1, 2, 3 i oz 1, 2, 3 i cc 1, 2, 3 switching characteristics parameter subgroups t pd 9, 10, 11 t co 9, 10, 11 t s 9, 10, 11 t h 9, 10, 11 package diagrams 20-lead (300-mil) cerdip d6 mil-std-1835 d-8 config. a 51-80029-**
palce16v8 document #: 38-03025 rev. *a page 11 of 13 package diagrams (continued) 20-lead plastic leaded chip carrier j61 51-85000-*a 20-square leadless chip carrier l61 51-80049-**
palce16v8 document #: 38-03025 rev. *a page 12 of 13 ? cypress semiconductor corporation, 2004. the information contained herein is subject to change without notice. cypress semic onductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or ot her rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agr eement with cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to re sult in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manu facturer assumes all risk of such use and in doing so indemni fies cypress against all charges. ultra37000 is a trademark of cypress semico nductor corporation. pal is a register ed trademark of advanced micro devices, inc. all products and company names mentioned in this document may be the trademarks of their respective holders. package diagrams (continued) 51-85011-*a 20-lead (300-mil) molded dip p5
palce16v8 document #: 38-03025 rev. *a page 13 of 13 document history page document title: palce16v8 flash erasable reprogrammable cmos pal ? device document number: 38-03025 rev. ecn no. issue date orig. of change description of change ** 106370 07/11/01 szv change from spec number: 38-00364 to 38-03025 *a 213375 see ecn fsg added note to title page: ?use ultra37000 for all new designs?

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